VHDL Verification Course

Using Transaction Logs

The purpose of this section is to show how to use transaction logs and to demonstrate why they are useful. First the usefulness shall be demonstrated.

Below are the requirements for two output signals of a device:

Parameter Description Min Max Unit

t_{SU_W} Setup time for W asserted 6 - ns

t_{SU_R} Setup time for R asserted 5 - ns

In this example a circuit has been synthesized already, and the simulation shall verify the VHDL description of the synthesized design. The following process shall check whether the timing requirements on the pins R and W are fulfilled. (The assumption of this test is that the design will execute write and read accesses alternatingly.)

        timing_check: process
        
           variable w_asserted: time;
           variable r_asserted: time;
        
           begin
        
           -- wait for DUT to be reset
           wait until RST = '1';
           wait until RST = '0';
             
           -- verify write access                     
           wait until W = '0';
           w_asserted := now;
           wait until W = '1';
        
           assert (now - w_asserted) >= tSU_W
             report "E@TB: W setup time too short"
             severity Error;
             
             
           -- verify read access                      
           wait until R = '0';
           r_asserted := now;
           wait until R = '1';  
        
           assert (now - r_asserted) >= tSU_R
             report "E@TB: R setup time too short"
             severity Error;
             
        end process timing_check;

Here is the description of the circuit's timing behaviour:

        -- description of the timing behaviour
        -- of the DUT implemenation            
        dut: process
        
           begin
        
           W <= '1';
           R <= '1';
        
           wait until RST = '1';
           wait until RST = '0';
        
           wait for 10 ns;
        
           -- write access
           W <= '0', '1' after 8 ns;
           wait for 10 ns;
        
           -- read access
           R <= '0', '1' after 9 ns;
           wait for 10 ns;
        
           -- write access
           W <= '0', '1' after 7 ns;
           wait for 10 ns;
        
           -- read access
           R <= '0', '1' after 4 ns; -- this is a violation we want to detect
           wait for 10 ns;
        
           -- write access
           W <= '0', '1' after 8 ns;
           wait for 10 ns;
        
           wait;
        
        end process dut;

As can be seen, the circuit does not meet the requirements. The second read pulse is too short. A simulation results in the following output, however:

        VSIM 26> run -all
        VSIM 27>

Closer examination of the timing_check process reveals that it contains an error causing it to verify only one write and one read access, as it won't progress after the read unless a second reset pulse occurs. However the simulation output is exactly as would be expected for a correctly functioning circuit.

This kind of error is not infrequent and can be avoided by using transaction logs. This is shown in the next section.

Below are the files which have been simulated in this section:

txt_util.vhd hang.vhd

Parameter	Description	Min	Max	Unit
t_{SU_W}	Setup time for W asserted	6	-	ns
t_{SU_R}	Setup time for R asserted	5	-	ns